Please check void rt_hw_mmu_init(void) in /libcpu/aarch64/common/mmu.c
And ARM spec for SCTLR_EL1 register details :-)
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hope it helps you.
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Thank you for your reply, and it is really helpful. I have checked the register and managed to disable DCache. However one thing I am curious, are we able to disable L2 cache only specifically? Thank you